华为何庭波"韬定律"论文发布，逻辑折叠技术提升芯片性能

No Dependence on New Photolithography! Kirin 2027, Ascend 990 Chips on the Way, Huawei's He Tingbo Unveils Key Points of "Tao (τ) Law" Paper - IT Home

Thanks to the tip from IT Home user Growing Under the Red Flag!

IT Home May 25 report: At today's International Conference on Circuits and Systems (ISCAS 2026), Huawei Director and President of Semiconductor Business Division, He Tingbo, officially presented the "Tao (τ) Law." The upcoming Kirin mobile chip this autumn will率先采用 LogicFolding technology, significantly boosting performance.

Additionally, He Tingbo's paper titled "A Time Scaling Theory for Multi-Layer Electronic Systems" was submitted to the Chinese Academy of Sciences' preprint platform today, detailing the "Tao Law" and outlining Huawei's future chip development plans.

According to the paper, He Tingbo believes that the "geometric era" in the chip industry, where the goal was to make transistors smaller, has ended. The current mainstream "Moore's Law," which focuses only on time (the number of transistors that can be accommodated on an integrated circuit approximately doubles every 18 to 24 months, with performance also doubling), and the era where each layer is independently optimized and time is a residual factor, have also ended.

The first production-scale test of the "Tao Law" will be conducted on mobile devices. He Tingbo stated that a smartphone SoC is a rare case where a single chip constitutes the entire system. Multi-slot parallelism is unavailable; there is no thousand-node architecture to mask slow connections. All performance provided to users comes from a single chip, with power consumption being just a few watts and constrained by the thermal limits set by handheld device form factors.

After 2020, when access to advanced nodes was restricted, the actual issue became: how to continuously achieve generational performance improvements on a single chip with a fixed node? The solution that emerged is LogicFolding.

LogicFolding is a design method that divides digital, analog, and storage circuits into vertically stacked active layers to jointly optimize performance, power consumption, and area according to the principle of time scaling.

Test results on the Kirin 2026 chip show:

• Transistor density increased in stages from 155 MTr/mm² to 238 MTr/mm² within a single generation, an improvement that would have taken three years of geometric scaling previously.

• The core energy efficiency of the SoC improved by 41%, with the maximum clock frequency increasing by nearly 13%.

• The high-speed global network-on-chip (NoC) data paths built between upper and lower layers reduced data path area by 55% and improved power delivery stability.

• An independent post-silicon clock skew adjustment scheme contributed more than 5% to SoC performance.

• In SRAM, where access speed, energy per bit, and area are highly dependent on word line and bit line length, LogicFolding shortened critical paths, reduced energy per bit, and increased operating frequency by over 40%.

• On a typical processing core, a dual-layer folding architecture reduced the number of clock buffers by more than 50%, clock skew by 25%, and wiring length by about 30%.

The paper notes that these gains were achieved at a fixed device node, not through new photolithography process steps, but by topologically reorganizing logic distribution in three-dimensional space.

It is worth noting that the LogicFolding used in Kirin 2026 was deliberately set to be conservative, with hybrid bonding spacing reaching 1.5 μm, and folding applied selectively to critical paths rather than throughout the entire design.

Nonetheless, the CPU core frequency of Kirin 2026 reached 3.1 GHz this year, with the maximum clock frequency increasing by nearly 13%.

The paper also indicates that LogicFolding is expected to evolve from local critical path folding to full-scale, multi-layer folding—three, four, or even more active layers per package—from 2026 to 2035. Transistor density is projected to reach 400 MTr/mm² or higher. Simultaneously, LogicFolding enables Kirin chips to significantly increase CPU core frequency, laying the groundwork for achieving 4 GHz and above. This roadmap is feasible and economically viable.

IT Home found two key points of interest in the table:

• The subsequent naming of Kirin chips, referred to in the paper as Kirin 2026, 2027, 2028, 2029, is unclear whether they are codenames or if Kirin chips might adopt a new naming convention.

• In the chip status column, apart from the Kirin 2026 chip to be released this year, next year's Kirin 2027 chip is marked as Silicon status, indicating substantial progress; while Kirin 2028 and 2029 chips remain in Pre-silicon (pre-silicon) status.

The paper also mentions the future roadmap for AI chips. By around 2030, AI accelerators (Ascend SuperPoD series—Ascend 910C in 2025, Ascend 950 in 2026, and subsequent 990) will rely on a combination of mature technologies: chiplets, 2.5D fan-out packaging, and 3D stacking via micro-bumps and standard pitch hybrid bonding.

Around 2030, Ascend 990 will introduce LogicFolding in the AI accelerator category, with hardware integration expected to increase by more than 100 times by 2035.

IT Home附论文链接:

https://chinaxiv.org/abs/202605.00224

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