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Qwen(@Alibaba_Qwen)

🚀 Introducing FlashQLA: high-performance linear attention kernels built on TileLang. ⚡ 2–3× forwar...

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🚀 Introducing FlashQLA: high-performance linear attention kernels built on TileLang.

⚡ 2–3× forwar...
AI 深度提炼
  • FlashQLA实现了2-3倍前向加速和2倍后向加速。
  • 采用门控驱动的自动片内CP和硬件友好的代数重构。
  • 特别适用于TP设置、小型模型和长上下文工作负载。

结构提纲

AI 替你读一遍后整理出的核心层级。

  1. 介绍FlashQLA及其主要性能提升。

  2. 详细说明FlashQLA的关键技术,如门控驱动的自动片内CP和硬件友好的代数重构。

  3. 讨论FlashQLA在不同场景下的性能优势,特别是TP设置、小型模型和长上下文工作负载。

  4. 提供FlashQLA的博客链接和GitHub代码库。

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  • FlashQLA: 高性能线性注意力内核

金句 / Highlights

值得收藏与分享的关键句。

  • 🚀 Introducing FlashQLA: high-performance linear attention kernels built on TileLang.

    第 1 段

    下载金句卡 PNG
  • ⚡ 2–3× forward speedup. 2× backward speedup.

    第 1 段

    下载金句卡 PNG
  • 💻 Purpose-built for agentic AI on your personal devices.

    第 1 段

    下载金句卡 PNG
  • 💡Key insights: 1. Gate-driven automatic intra-card CP. 2. Hardware-friendly algebraic reformulation. 3. TileLang fused warp-specialized kernels.

    第 2 段

    下载金句卡 PNG
#AI#性能优化#TileLang
打开原文

⚡ 2–3× forward speedup. 2× backward speedup. 💻 Purpose-built for agentic AI on your personal devices.

💡Key insights: 1. Gate-driven automatic intra-card CP. 2. Hardware-friendly algebraic https://t.co/pA9HCHwFZw" / X

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![Image 1: Square profile picture](https://x.com/Alibaba_Qwen)

Qwen

@Alibaba_Qwen

!Image 2: 🚀 Introducing FlashQLA: high-performance linear attention kernels built on TileLang. !Image 3: ⚡ 2–3× forward speedup. 2× backward speedup. !Image 4: 💻 Purpose-built for agentic AI on your personal devices. !Image 5: 💡Key insights: 1. Gate-driven automatic intra-card CP. 2. Hardware-friendly algebraic reformulation. 3. TileLang fused warp-specialized kernels. FlashQLA boosts SM utilization via automatic intra-device CP. The gains are especially pronounced for TP setups, small models, and long-context workloads. Instead of fusing the entire GDN flow into a single kernel, we split it into two kernels optimized for CP and backward efficiency. At large batch sizes this incurs extra memory I/O overhead vs. a fully fused approach, but it delivers better real-world performance on edge devices and long-context workloads. The backward pass was the hardest part: we built a 16-stage warp-specialized pipeline under extremely tight on-chip memory constraints, ultimately achieving 2×+ kernel-level speedups. We hope this is useful to the community!!Image 6: 🫶!Image 7: 🫶 Learn more: !Image 8: 📖 Blog: qwen.ai/blog?id=flashq!Image 9: 💻 Code: github.com/QwenLM/FlashQLA

![Image 10: Image](https://x.com/Alibaba_Qwen/status/2049462666734026923/photo/1)

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12:15 PM · Apr 29, 2026

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